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RTAS
2015
IEEE
9 years 10 months ago
A predictable and command-level priority-based DRAM controller for mixed-criticality systems
—Mixed-criticality systems have tasks with different criticality levels running on the same hardware platform. Today’s DRAM controllers cannot adequately satisfy the often con...
Hokeun Kim, David Broman, Edward A. Lee, Michael Z...
92
Voted
RTAS
2015
IEEE
9 years 10 months ago
When thermal control meets sensor noise: analysis of noise-induced temperature error
—Thermal control is critical for real-time systems as overheated processors can result in serious performance degradation or even system breakdown due to hardware throttling. The...
Dohwan Kim, Kyung-Joon Park, Yongsoon Eun, Sang Hy...
88
Voted
RTAS
2015
IEEE
9 years 10 months ago
AUTOBEST: a united AUTOSAR-OS and ARINC 653 kernel
—This paper presents AUTOBEST, a united AUTOSAR-OS and ARINC 653 RTOS kernel that addresses the requirements of both automotive and avionics domains. We show that their domain-sp...
Alexander Zuepke, Marc Bommert, Daniel Lohmann
85
Voted
RTAS
2015
IEEE
9 years 10 months ago
Multicore scheduling of parallel real-time tasks with multiple parallelization options
—Past researches on multicore scheduling assume that a computational unit has already been parallelized into a prefixed number of threads. However, with recent technologies such...
Jihye Kwon, Kang-Wook Kim, Sangyoun Paik, Jihwa Le...
84
Voted
RTAS
2015
IEEE
9 years 10 months ago
Top-down and bottom-up multi-level cache analysis for WCET estimation
—In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidatio...
Zhenkai Zhang, Xenofon D. Koutsoukos
Embedded Systems
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