2488 search results - page 24 / 498 » An improvement in formal verification |
123
Voted
JSA
2008
15 years 9 days ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
111
Voted
CORR
2011
Springer
14 years 7 months ago
2011
Springer
— In recent times, many protocols have been proposed to provide security for various information and communication systems. Such protocols must be tested for their functional cor...
89
Voted
MJ
2006
15 years 22 days ago
2006
In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
96
Voted
CADE
2002
Springer
16 years 1 months ago
2002
Springer
Decision procedures for combinations of theories are at the core of many modern theorem provers such as ACL2, Ehdm, PVS, SIMPLIFY, the Stanford Pascal Verifier, STeP, SVC, and Z/Ev...
127
Voted
DAC
1996
ACM
15 years 5 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...