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2000
IEEE
99views Hardware» more  DATE 2000»
13 years 10 months ago
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
ET
2002
115views more  ET 2002»
13 years 6 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 12 days ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...