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SAC
1997
ACM
15 years 7 months ago
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
VLSID
1995
IEEE
112views VLSI» more  VLSID 1995»
15 years 7 months ago
An efficient automatic test generation system for path delay faults in combinational circuits
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
95
Voted
VLSID
1995
IEEE
107views VLSI» more  VLSID 1995»
15 years 7 months ago
Functional test generation for non-scan sequential circuits
Mandyam-Komar Srinivas, James Jacob, Vishwani D. A...