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ISCAPDCS
2001
15 years 5 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
FPL
2010
Springer
146views Hardware» more  FPL 2010»
15 years 2 months ago
Software Managed Distributed Memories in MPPAs
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
Robin Panda, Jimmy Xu, Scott Hauck
IPPS
2007
IEEE
15 years 10 months ago
Using an FPGA for Fast Bit Accurate SoC Simulation
In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
IFL
2003
Springer
15 years 9 months ago
Dynamic Chunking in Eden
Parallel programming generally requires awareness of the granularity and communication requirements of parallel subtasks, since without precaution, the overhead for parameter and r...
Jost Berthold
IPPS
1998
IEEE
15 years 8 months ago
Optimal Communication Performance on Fast Ethernet with GAMMA
Abstract. The current prototype of the Genoa Active Message MAchine GAMMA is a low-overhead, Active Messages-based inter-process communication layer implemented mainly at kernel le...
Giuseppe Ciaccio