Sciweavers

2048 search results - page 42 / 410
» Optimizing pipelines for power and performance
Sort
View
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
15 years 5 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
DAC
2003
ACM
16 years 25 days ago
Pushing ASIC performance in a power envelope
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kun...
INFOCOM
2006
IEEE
15 years 5 months ago
On the Performance of Joint Rate/Power Control with Adaptive Modulation in Wireless CDMA Networks
Abstract— Adaptive rate/power control schemes have great potential to increase the throughput of wireless CDMA networks. In this paper, we investigate the additional gains achiev...
Alaa Muqattash, Tao Shu, Marwan Krunz
CASES
2007
ACM
15 years 1 months ago
Facilitating compiler optimizations through the dynamic mapping of alternate register structures
Aggressive compiler optimizations such as software pipelining and loop invariant code motion can significantly improve application performance, but these transformations often re...
Chris Zimmer, Stephen Roderick Hines, Prasad Kulka...
NOMS
2008
IEEE
181views Communications» more  NOMS 2008»
15 years 6 months ago
Coordinated management of power usage and runtime performance
— With the continued growth of computing power and reduction in physical size of enterprise servers, the need for actively managing electrical power usage in large datacenters is...
Malgorzata Steinder, Ian Whalley, James E. Hanson,...