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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 3 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
83
Voted
CF
2007
ACM
15 years 2 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
92
Voted
ICLP
2010
Springer
15 years 2 months ago
A Logical Paradigm for Systems Biology (Invited Talk)
[6]. An SBML model can be interpreted in Biocham at three abstraction levels: • the Boolean semantics (asynchronuous Boolean state transitions on the presence/absence of molecule...
François Fages
93
Voted
CSUR
2006
147views more  CSUR 2006»
14 years 10 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan
CASES
2006
ACM
15 years 4 months ago
Methods for power optimization in distributed embedded systems with real-time requirements
Dynamic voltage scaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have st...
Razvan Racu, Arne Hamann, Rolf Ernst, Bren Mochock...