4794 search results - page 107 / 959 » Trust-Based Mechanism Design |
ATAL
2009
Springer
15 years 4 months ago
2009
Springer
Sensor nodes are often used to collect data from locations inaccessible or hazardous for humans. As they are not under normal supervision, these nodes are particularly susceptible...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
CF
2010
ACM
15 years 3 months ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
DSD
2010
IEEE
14 years 10 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
ET
2002
14 years 9 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...