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» Uncertainty-aware circuit optimization

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DAC
1995
ACM

127views Computer Architecture» more DAC 1995»

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

15 years 1 months ago

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Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...

Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...

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ASPDAC
2007
ACM

117views Hardware» more ASPDAC 2007»

Short-Circuit Compiler Transformation: Optimizing Conditional Blocks

15 years 1 months ago

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Abstract-- We present the short-circuit code transformation technique, intended for embedded compilers. The transformation technique optimizes conditional blocks in high-level prog...

Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau

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VTS
1998
IEEE

97views Hardware» more VTS 1998»

On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits

15 years 1 months ago

Download www.cad.polito.it

This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...

Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...

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ICCAD
1997
IEEE

101views Hardware» more ICCAD 1997»

Optimal wire and transistor sizing for circuits with non-tree topology

15 years 1 months ago