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» Very Compact FPGA Implementation of the AES Algorithm
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SLIP
2009
ACM
15 years 4 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
101
Voted
CODES
2003
IEEE
15 years 2 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
PLDI
2006
ACM
15 years 3 months ago
The Compressor: concurrent, incremental, and parallel compaction
The widely used Mark-and-Sweep garbage collector has a drawback in that it does not move objects during collection. As a result, large long-running realistic applications, such as...
Haim Kermany, Erez Petrank
GRAPHITE
2007
ACM
15 years 1 months ago
Compact and efficient generation of radiance transfer for dynamically articulated characters
We present a data-driven technique for generating the precomputed radiance transfer vectors of an animated character as a function of its joint angles. We learn a linear model for...
Derek Nowrouzezahrai, Patricio D. Simari, Evangelo...
GECCO
2007
Springer
155views Optimization» more  GECCO 2007»
15 years 3 months ago
Towards billion-bit optimization via a parallel estimation of distribution algorithm
This paper presents a highly efficient, fully parallelized implementation of the compact genetic algorithm (cGA) to solve very large scale problems with millions to billions of va...
Kumara Sastry, David E. Goldberg, Xavier Llor&agra...