Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors

- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serious challenges. Multiprocessors-on-a-ProgrammableChip (MPoPCs), which integrate both softwareprogrammability and hardware-reconfigurability, provide substantial flexibility that can result in programming ease and high performance. This paper presents an application-oriented system design methodology for HERA (HEterogeneous Reconfigurable Architecture), an in-house developed MPoPC that targets applications involving large matrices. HERA is a mixed computing-mode multiprocessor supporting simultaneous execution in SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data), and multiple-SIMD for chosen groups of processors. Given an application with specific energy-performance objectives, our design methodology aims to customize HERA to match the diverse computation and communication cha...

• Type: Conference
• Year: 2007
• Where: ERSA
• Authors: Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
• Keywords: Design Methodology, ERSA 2007, Floating-point Scientific Applications, Hardware, Hera