85 search results - page 1 / 17 » Designing Memory Subsystems Resilient to Process Variations |
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
TVLSI
2008
13 years 4 months ago
2008
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
In this paper we study the impact of sharing memory resources on five Google datacenter applications: a web search engine, bigtable, content analyzer, image stitching, and protoc...