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DATE
2009
IEEE

TRAM: A tool for Temperature and Reliability Aware Memory Design

9 years 5 months ago
TRAM: A tool for Temperature and Reliability Aware Memory Design
— Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system’s power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.
Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurd
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir
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