65 search results - page 1 / 13 » A low dynamic power and low leakage power 90-nm CMOS square-... |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on l...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...