22 search results - page 1 / 5 » An efficient automatic test generation system for path delay... |
VLSID
1995
IEEE
13 years 8 months ago
1995
IEEE
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...