20 search results - page 2 / 4 » BIST Based Interconnect Fault Location for FPGAs |
ATS
1998
IEEE
13 years 9 months ago
1998
IEEE
Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mai...
ET
2006
13 years 4 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
FPGA
2000
ACM
13 years 8 months ago
2000
ACM
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...