5 search results - page 1 / 1 » High Defect Coverage with Low-Power Test Sequences in a BIST... |
DT
2002
13 years 4 months ago
2002
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
ET
2002
13 years 4 months ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...