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» On Improving Diagnostic Test Generation for Scan Chain Failu...
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ATS
2009
IEEE
135views Hardware» more  ATS 2009»
14 years 18 hour ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...
ITC
2003
IEEE
143views Hardware» more  ITC 2003»
13 years 10 months ago
Designed -in-diagnostics: A new optical method
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
Keneth R. Wilsher
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
13 years 9 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
ITC
2002
IEEE
94views Hardware» more  ITC 2002»
13 years 10 months ago
Techniques to Reduce Data Volume and Application Time for Transition Test
1 Scan based transition tests are added to improve the detection of speed failures using scan tests. Empirical data suggests that both data volume and application time, for transi...
Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, P...