7 search results - page 1 / 2 » Power and slew-aware clock network design for through-silico... |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...