49 search results - page 9 / 10 » Reduction of Power Dissipation during Scan Testing by Test V... |
VLSID
2005
IEEE
13 years 11 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
ATS
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
IOLTS
2008
IEEE
14 years 5 days ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
DFT
2003
IEEE
13 years 11 months ago
2003
IEEE
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...