17 search results - page 1 / 4 » Register Allocation and Binding for Low Power |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
TVLSI
2010
12 years 11 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...