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    DAC
    1997
    ACM
    75views Computer Architecture» more  DAC 1997»
    Efficient Testing of Clock Regenerator Circuits in Scan Designs
    13 years 9 months ago
    Efficient Testing of Clock Regenerator Circuits in Scan Designs
    Download  www.cs.york.ac.uk
    Rajesh Raina, Robert Bailey, Charles Njinda, Rober...
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    DAC
    1997
    ACM
    86views Computer Architecture» more  DAC 1997»
    A Hybrid Algorithm for Test Point Selection for Scan-Based BIST
    13 years 9 months ago
    A Hybrid Algorithm for Test Point Selection for Scan-Based BIST
    Download  cadlab.ece.ucsb.edu
    Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Su...
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    ISCAS
    2005
    IEEE
    129views Hardware» more  ISCAS 2005»
    A reconfigurable architecture for scanning biosequence databases
    13 years 11 months ago
    A reconfigurable architecture for scanning biosequence databases
    Download  www3.ntu.edu.sg
    —Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
    Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
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    VTS
    2005
    IEEE
    106views Hardware» more  VTS 2005»
    Segmented Addressable Scan Architecture
    13 years 11 months ago
    Segmented Addressable Scan Architecture
    Download  www-crc.stanford.edu
    This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
    Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
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    DAC
    2005
    ACM
    93views Computer Architecture» more  DAC 2005»
    Secure scan: a design-for-test architecture for crypto chips
    14 years 6 months ago
    Secure scan: a design-for-test architecture for crypto chips
    Download  www.inf.ethz.ch
    Bo Yang, Kaijie Wu, Ramesh Karri
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