15 search results - page 2 / 3 » Test-access mechanism optimization for core-based three-dime... |
ET
2002
13 years 5 months ago
2002
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
DATE
2009
IEEE
14 years 1 days ago
2009
IEEE
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...