40 search results - page 2 / 8 » Testing of a Highly Reconfigurable Processor Core for Depend... |
FPL
2006
Springer
13 years 9 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
FCCM
2004
IEEE
13 years 9 months ago
2004
IEEE
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
ERSA
2004
13 years 6 months ago
2004
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...