9 search results - page 2 / 2 » Yield enhancements of design-specific FPGAs |
FPL
2006
Springer
13 years 9 months ago
2006
Springer
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
DAC
2011
ACM
12 years 5 months ago
2011
ACM
A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) arra...