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CVIU
2010
267views more  CVIU 2010»
8 years 1 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
IFIP12
2009
8 years 2 months ago
TELIOS: A Tool for the Automatic Generation of Logic Programming Machines
In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, wh...
Alexandros C. Dimopoulos, Christos Pavlatos, Georg...
FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
8 years 2 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna
IPPS
2010
IEEE
8 years 2 months ago
A GPU-inspired soft processor for high-throughput acceleration
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
Jeffrey Kingyens, J. Gregory Steffan
FPL
2010
Springer
170views Hardware» more  FPL 2010»
8 years 2 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
FPL
2010
Springer
168views Hardware» more  FPL 2010»
8 years 2 months ago
Pipelined FPGA Adders
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. Thi...
Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasc...
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
8 years 2 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
CSREAESA
2010
8 years 2 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
8 years 2 months ago
A PUF design for secure FPGA-based embedded systems
The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy...
Jason Helge Anderson
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