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FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
8 years 5 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
ERSA
2003
147views Hardware» more  ERSA 2003»
8 years 5 months ago
Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications
Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an applicati...
Timothy F. Oliver, Douglas L. Maskell
ERSA
2007
174views Hardware» more  ERSA 2007»
8 years 5 months ago
High-Level Specification of Runtime Reconfigurable Designs
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
Stephen D. Craven, Peter M. Athanas
FPL
2008
Springer
175views Hardware» more  FPL 2008»
8 years 5 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
8 years 5 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
8 years 5 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong
FPGA
2008
ACM
163views FPGA» more  FPGA 2008»
8 years 5 months ago
High-quality, deterministic parallel placement for FPGAs on commodity hardware
In this paper, we describe the application of two parallelization strategies to the Quartus II FPGA placer. The first
Adrian Ludwin, Vaughn Betz, Ketan Padalia
FPGA
2008
ACM
191views FPGA» more  FPGA 2008»
8 years 5 months ago
A hardware framework for the fast generation of multiple long-period random number streams
Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality ps...
Ishaan L. Dalal, Deian Stefan
FPGA
2008
ACM
163views FPGA» more  FPGA 2008»
8 years 5 months ago
TORCH: a design tool for routing channel segmentation in FPGAs
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
Mingjie Lin, Abbas El Gamal
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