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VLSISP
2010
205views more  VLSISP 2010»
8 years 2 months ago
Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA
— This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, s...
Dimitris G. Bariamis, Dimitris Maroulis, Dimitrios...
LATINCRYPT
2010
8 years 2 months ago
Accelerating Lattice Reduction with FPGAs
We describe an FPGA accelerator for the Kannan–Fincke– Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementati...
Jérémie Detrey, Guillaume Hanrot, Xa...
VLSISP
2002
199views more  VLSISP 2002»
8 years 4 months ago
Evaluation of CORDIC Algorithms for FPGA Design
Abstract. This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the...
Javier Valls, Martin Kuhlmann, Keshab K. Parhi
TCAD
2002
134views more  TCAD 2002»
8 years 4 months ago
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
Ian G. Harris, Russell Tessier
TVLSI
1998
123views more  TVLSI 1998»
8 years 4 months ago
On-line fault detection for bus-based field programmable gate arrays
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
N. R. Shnidman, William H. Mangione-Smith, Miodrag...
TC
1998
8 years 4 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt
DT
1998
85views more  DT 1998»
8 years 4 months ago
How Much Logic Should Go in an FPGA Logic Block?
The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related ...
Vaughn Betz, Jonathan Rose
JUCS
2000
135views more  JUCS 2000»
8 years 4 months ago
The Price of Routing in FPGAs
: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to r...
Florent de Dinechin
MAM
2007
157views more  MAM 2007»
8 years 4 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
TVLSI
2008
111views more  TVLSI 2008»
8 years 4 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
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