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ICS
1995
Tsinghua U.
13 years 8 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
13 years 8 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
CODES
2001
IEEE
13 years 8 months ago
Towards effective embedded processors in codesigns: customizable partitioned caches
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
Peter Petrov, Alex Orailoglu
CASES
2001
ACM
13 years 8 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...
DSD
2006
IEEE
174views Hardware» more  DSD 2006»
13 years 8 months ago
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
Alokika Dash, Peter Petrov
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
13 years 8 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
CF
2006
ACM
13 years 8 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 8 months ago
Low Static-Power Frequent-Value Data Caches
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
Chuanjun Zhang, Jun Yang 0002, Frank Vahid
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
13 years 8 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ARCS
2006
Springer
13 years 8 months ago
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...
Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien...