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DATE
2002
IEEE
101views Hardware» more  DATE 2002»
13 years 9 months ago
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter
The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tool...
Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Mi...
DATE
2002
IEEE
124views Hardware» more  DATE 2002»
13 years 9 months ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
13 years 9 months ago
Generalized Early Evaluation in Self-Timed Circuits
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
Mitchell A. Thornton, Kenneth Fazel, Robert B. Ree...
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
13 years 9 months ago
Fast Method to Include Parasitic Coupling in Circuit Simulations
S-parameter based circuit simulators are used a lot for the design of microwave circuits. The accuracy of these simulators is limited by the fact that they do not take the electro...
B. L. A. Van Thielen, G. A. E. Vandenbosch
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
13 years 9 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
13 years 9 months ago
Macromodeling of Digital I/O Ports for System EMC Assessment
This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A ...
Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio...
DATE
2002
IEEE
130views Hardware» more  DATE 2002»
13 years 9 months ago
Assigning Program and Data Objects to Scratchpad for Energy Reduction
The number of embedded systems is increasing and a remarkable percentage is designed as mobile applications. For the latter, the energy consumption is a limiting factor because of...
Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter M...
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
13 years 9 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
DATE
2002
IEEE
151views Hardware» more  DATE 2002»
13 years 9 months ago
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These set...
Robert Schwencker, Frank Schenkel, Michael Pronath...
DATE
2002
IEEE
88views Hardware» more  DATE 2002»
13 years 9 months ago
Internet-Based Collaborative Test Generation with MOSCITO
André Schneider, Karl-Heinz Diener, Eero Iv...