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ASPLOS
2008
ACM
13 years 6 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 8 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
13 years 8 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ISCA
1989
IEEE
120views Hardware» more  ISCA 1989»
13 years 9 months ago
Comparing Software and Hardware Schemes For Reducing the Cost of Branches
Pipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instru...
Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
13 years 9 months ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
13 years 9 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
ISCA
1998
IEEE
108views Hardware» more  ISCA 1998»
13 years 9 months ago
Pipeline Gating: Speculation Control for Energy Reduction
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
Srilatha Manne, Artur Klauser, Dirk Grunwald
ICCAD
1998
IEEE
74views Hardware» more  ICCAD 1998»
13 years 9 months ago
Synthesis of application specific instructions for embedded DSP software
Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Che...
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 9 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan...
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
13 years 9 months ago
Selective Value Prediction
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
Brad Calder, Glenn Reinman, Dean M. Tullsen