Sciweavers

ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
13 years 10 months ago
Low power repeaters driving RLC interconnects with delay and bandwidth constraints
— Interconnect plays an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power,...
Guoqing Chen, Eby G. Friedman
ISCAS
2005
IEEE
117views Hardware» more  ISCAS 2005»
13 years 10 months ago
Electrical and optical on-chip interconnects in scaled microprocessors
Abstract— Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper ...
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas...
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
13 years 10 months ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
GLVLSI
2005
IEEE
199views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Interconnect delay minimization through interlayer via placement in 3-D ICs
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
Vasilis F. Pavlidis, Eby G. Friedman
SLIP
2006
ACM
13 years 10 months ago
Generation of design guarantees for interconnect matching
Manufacturable design requires matching of interconnects which have equal nominal dimensions. New design rules are projected to bring guarantee rules for interconnect matching. In...
Andrew B. Kahng, Rasit Onur Topaloglu
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
13 years 10 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
13 years 10 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
ETS
2006
IEEE
113views Hardware» more  ETS 2006»
13 years 10 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
13 years 10 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...