Sciweavers

ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
13 years 11 months ago
Impact of Gate-Length Biasing on Threshold-Voltage Selection
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
ISQED
2006
IEEE
142views Hardware» more  ISQED 2006»
13 years 11 months ago
Constructing Current-Based Gate Models Based on Existing Timing Library
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
Andrew B. Kahng, Bao Liu, Xu Xu
ISQED
2006
IEEE
108views Hardware» more  ISQED 2006»
13 years 11 months ago
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
This paper proposes a novel method for analyzing large onchip power delivery networks via a stochastic moment matching (SMM) method. The proposed method extends the existing direc...
Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
13 years 11 months ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
ISQED
2006
IEEE
75views Hardware» more  ISQED 2006»
13 years 11 months ago
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
Interconnects are becoming an increasing problem from both performance and power consumption perspective in fu
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vi...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 11 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
ISQED
2006
IEEE
103views Hardware» more  ISQED 2006»
13 years 11 months ago
Efficient Model Update for General Link-Insertion Networks
Zhuo Feng, Peng Li, Jiang Hu
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
13 years 11 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 11 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...
ISQED
2006
IEEE
78views Hardware» more  ISQED 2006»
13 years 11 months ago
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
Andrew Havlir, David Z. Pan