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DAC
1995
ACM
8 years 9 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
DAC
2004
ACM
8 years 10 months ago
A methodology to improve timing yield in the presence of process variations
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wa...
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
8 years 10 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
VLSID
1999
IEEE
87views VLSI» more  VLSID 1999»
8 years 10 months ago
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
Vishwani D. Agrawal, Michael L. Bushnell, Ganapath...
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
8 years 10 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
8 years 10 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
ISPD
2003
ACM
89views Hardware» more  ISPD 2003»
8 years 11 months ago
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
Andrew B. Kahng, Xu Xu
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
8 years 11 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
ICCS
2004
Springer
8 years 11 months ago
On Balancing Delay and Cost for Routing Paths
Abstract. The distributed adaptive routing is the typical routing algorithm that is used in the current Internet. The path cost of the least delay (LD) path is relatively more expe...
Moonseong Kim, Young-Cheol Bang, Hyunseung Choo
WWIC
2007
Springer
102views Communications» more  WWIC 2007»
9 years 9 days ago
SCTP Performance Issue on Path Delay Differential
This paper studies the effect of path delay on SCTP performance. It focuses on the SCTP fast retransmit algorithm and demonstrates that the performance in the current retransmissio...
Yuansong Qiao, Enda Fallon, Liam Murphy, John Murp...
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