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    FCCM
    2007
    IEEE
    485views VLSI» more  FCCM 2007»
    Low-Cost Stereo Vision on an FPGA
    13 years 8 months ago
    Low-Cost Stereo Vision on an FPGA
    Download  www.chrismurf.com
    We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation uti...
    Chris Murphy, Daniel Lindquist, Ann Marie Rynning,...
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    FCCM
    2007
    IEEE
    122views VLSI» more  FCCM 2007»
    Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
    13 years 8 months ago
    Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
    Download  www.coe.uncc.edu
    While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
    Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
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    DFT
    2007
    IEEE
    152views VLSI» more  DFT 2007»
    TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
    13 years 8 months ago
    TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
    Download  www.dresd.org
    This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
    Cristiana Bolchini, Antonio Miele, Marco D. Santam...
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    DFT
    2007
    IEEE
    86views VLSI» more  DFT 2007»
    Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
    13 years 8 months ago
    Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
    Download  pub2.db.tokushima-u.ac.jp
    Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa,...
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    VLSID
    1994
    IEEE
    113views VLSI» more  VLSID 1994»
    A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
    13 years 8 months ago
    A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
    Download  eprints.iisc.ernet.in
    In this paper, we propose an architecture synthesis methodolog `to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate A m y s (FP...
    G. N. Rathna, S. K. Nandy, K. Parthasarathy
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    VLSID
    1994
    IEEE
    82views VLSI» more  VLSID 1994»
    High Speed Digital Filtering on SRAM-Based FPGAs
    13 years 8 months ago
    High Speed Digital Filtering on SRAM-Based FPGAs
    Download  eprints.iisc.ernet.in
    A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghosha...
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    VLSID
    1994
    IEEE
    124views VLSI» more  VLSID 1994»
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    13 years 8 months ago
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    Download  www.cs.kent.edu
    In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
    Samit Chaudhuri, Robert A. Walker
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    VLSID
    1994
    IEEE
    84views VLSI» more  VLSID 1994»
    Energy Efficient Programmable Computation
    13 years 8 months ago
    Energy Efficient Programmable Computation
    Download  bwrc.eecs.berkeley.edu
    : This paper describes techniques for energy efficient implementation of programmable computation. consumption in programmable computation can be substantiallvlowered with nolossin...
    Anantha Chandrakasan, Mani B. Srivastava, Robert W...
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    VLSID
    1994
    IEEE
    151views VLSI» more  VLSID 1994»
    A CORDIC Based Programmable DXT Processor Array
    13 years 8 months ago
    A CORDIC Based Programmable DXT Processor Array
    Download  eprints.iisc.ernet.in
    A CORDIC based processor array which can be programmed by switch settings to compute the Discrete Hariley, Cosine or Sine lhnsforms or their inverses is described. Through a novel...
    V. K. Anuradha, V. Visvanathan
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    VLSID
    1994
    IEEE
    103views VLSI» more  VLSID 1994»
    GLOVE: A Graph-Based Layout Verifier
    13 years 8 months ago
    GLOVE: A Graph-Based Layout Verifier
    Download  chair36.msiu.ru
    Cyrus Bamji, Jonathan Allen
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