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    FCCM
    2009
    IEEE
    204views VLSI» more  FCCM 2009»
    Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
    13 years 8 months ago
    Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
    Download  www.esa.informatik.tu-darmstadt.de
    Geometric algebra (GA) is a mathematical framework that allows the compact description of geometric relationships and algorithms in many fields of science and engineering. The exe...
    Holger Lange, Florian Stock, Andreas Koch, Dietmar...
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    FCCM
    2009
    IEEE
    316views VLSI» more  FCCM 2009»
    An FPGA Implementation for Solving Least Square Problem
    13 years 8 months ago
    An FPGA Implementation for Solving Least Square Problem
    Download  www.ece.utk.edu
    This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...
    Depeng Yang, Gregory D. Peterson, Husheng Li, Junq...
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    FCCM
    2009
    IEEE
    136views VLSI» more  FCCM 2009»
    Accelerating Cosmological Data Analysis with FPGAs
    13 years 8 months ago
    Accelerating Cosmological Data Analysis with FPGAs
    Download  www.ncsa.illinois.edu
    Volodymyr V. Kindratenko, Robert J. Brunner
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    FCCM
    2009
    IEEE
    106views VLSI» more  FCCM 2009»
    Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
    13 years 8 months ago
    Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
    Download  www.comp.nus.edu.sg
    Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
    Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
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    FCCM
    2009
    IEEE
    115views VLSI» more  FCCM 2009»
    Multi-Core Architecture on FPGA for Large Dictionary String Matching
    13 years 8 months ago
    Multi-Core Architecture on FPGA for Large Dictionary String Matching
    Download  halcyon.usc.edu
    FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
    Qingbo Wang, Viktor K. Prasanna
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    FCCM
    2009
    IEEE
    134views VLSI» more  FCCM 2009»
    Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
    13 years 8 months ago
    Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
    Download  www.chrec.org
    Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
    Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
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    FCCM
    2009
    IEEE
    123views VLSI» more  FCCM 2009»
    Scalable High Throughput and Power Efficient IP-Lookup on FPGA
    13 years 8 months ago
    Scalable High Throughput and Power Efficient IP-Lookup on FPGA
    Download  halcyon.usc.edu
    Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
    Hoang Le, Viktor K. Prasanna
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    GLVLSI
    2007
    IEEE
    166views VLSI» more  GLVLSI 2007»
    Efficient pipelining for modular multiplication architectures in prime fields
    13 years 8 months ago
    Efficient pipelining for modular multiplication architectures in prime fields
    Download  www.cosic.esat.kuleuven.be
    This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
    Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
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    GLVLSI
    2007
    IEEE
    141views VLSI» more  GLVLSI 2007»
    A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
    13 years 8 months ago
    A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
    Download  web.it.kth.se
    he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
    Tarvo Raudvere, Ingo Sander, Axel Jantsch
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    GLVLSI
    2007
    IEEE
    162views VLSI» more  GLVLSI 2007»
    Utilizing custom registers in application-specific instruction set processors for register spills elimination
    13 years 8 months ago
    Utilizing custom registers in application-specific instruction set processors for register spills elimination
    Download  www.engr.uconn.edu
    Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
    Hai Lin, Yunsi Fei
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