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GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
13 years 10 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
GLVLSI
2007
IEEE
139views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Synthesis of irregular combinational functions with large don't care sets
A special logic synthesis problem is considered for Boolean functions which have large don’t care sets and are irregular. Here, a function is considered as irregular if the inpu...
Valentin Gherman, Hans-Joachim Wunderlich, R. D. M...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS ad...
Chichyang Chen, Paul Chow
GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Design of an UHF RFID transponder for secure authentication
RFID technology increases rapidly its applicability in new areas of interest without guaranteeing security and privacy issues. This paper presents a new architecture of an RFID tr...
Paolo Bernardi, Filippo Gandino, Bartolomeo Montru...
GLVLSI
2007
IEEE
152views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Optimization techniques for BDD-based bisimulation computation
Ralf Wimmer, Marc Herbstritt, Bernd Becker
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann