Sciweavers

ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
15 years 8 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
INFOCOM
1997
IEEE
15 years 8 months ago
Toward Formal TTCN-Based Test Execution
Ruibing Hao, Jianping Wu
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 8 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
ICCAD
1995
IEEE
96views Hardware» more  ICCAD 1995»
15 years 8 months ago
Delay optimal partitioning targeting low power VLSI circuits
Hirendu Vaishnav, Massoud Pedram