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EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
15 years 8 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
15 years 8 months ago
Semi-dynamic scheduling of synchronization-mechanisms
This paper presents a novel approach to scheduling of hardware supported synchronization operations. The optimization goal is to minimize the interation time of processes and thus...
Wolfgang Ecker
EURODAC
1995
IEEE
180views VHDL» more  EURODAC 1995»
15 years 8 months ago
Integration of VHDL into a system design environment
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
Ludwig Schwoerer, Matthias Lück, Hartmut Schr...