141
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EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
112
click to vote
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
140
click to vote
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
This paper addresses the problem of semantic heterogeneity between data representations with particular emphasis on CAD tool data representations. The combination of powerful mapp...
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
122
click to vote
EURODAC
1995
IEEE
15 years 8 months ago
1995
IEEE
The behaviour of a real-time system can be validated at the system level by means of a real-time operating system model in a VHDL simulation environment. The model consists of the...