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ISPD
2003
ACM
171views Hardware» more  ISPD 2003»
15 years 6 months ago
Timing driven force directed placement with physical net constraints
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tu...
ISPD
2003
ACM
151views Hardware» more  ISPD 2003»
15 years 6 months ago
Capturing crosstalk-induced waveform for accurate static timing analysis
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 6 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 6 months ago
Closed form expressions for extending step delay and slew metrics to ramp inputs
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
Chandramouli V. Kashyap, Charles J. Alpert, Frank ...
ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
15 years 6 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
Hardware
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