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MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 6 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 6 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 6 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
MICRO
2003
IEEE
155views Hardware» more  MICRO 2003»
15 years 6 months ago
Comparing Program Phase Detection Techniques
Detecting program phase changes accurately is an important aspect of dynamically adaptable systems. Three dynamic program phase detection techniques are compared – using instruc...
Ashutosh S. Dhodapkar, James E. Smith
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
15 years 6 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
Hardware
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