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GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 6 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 1 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
DFT
2003
IEEE
246views VLSI» more  DFT 2003»
15 years 6 months ago
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...
Konstantinos Rokas, Yiorgos Makris, Dimitris Gizop...
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
15 years 6 months ago
A novel 32-bit scalable multiplier architecture
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
Yeshwant Kolla, Yong-Bin Kim, John Carter
VLSI
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