291
click to vote
ISPD
14 years 16 days ago
2012 ACM 
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...
213
click to vote
ISPD
14 years 16 days ago
2012 ACM 
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
182
click to vote
ISPD
14 years 16 days ago
2012 ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
169
click to vote
ISPD
14 years 16 days ago
2012 ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
184
click to vote
ISPD
14 years 16 days ago
2012 ACM
Importance sampling is a popular approach to estimate rare event failures of SRAM cells. We propose to improve importance sampling by probability collectives. First, we use “Kul...
|
Hardware