224
click to vote
ARC
14 years 21 days ago
2012 Springer 
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
180
click to vote
ARC
14 years 21 days ago
2012 Springer 
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
144
Voted
ARC
14 years 21 days ago
2012 Springer
Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing...
|
Hardware