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205
Voted
ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
13 years 2 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
13 years 2 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
123
Voted
ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
13 years 2 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...
ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
13 years 2 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
13 years 2 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
Hardware
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