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ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
10 years 3 months ago
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits
Abstract— We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the unio...
Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoell...
ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
10 years 3 months ago
Modeling and optimization of low power resonant clock mesh
—Power consumption is becoming more critical in modern integrated circuit (IC) designs and clock network is one of the major contributors for on-chip power. Resonant clock has be...
Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang
ASPDAC
2015
ACM
17views Hardware» more  ASPDAC 2015»
10 years 3 months ago
An HDL-synthesized gated-edge-injection PLL with a current output DAC
– This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for ...
Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot...
ASPDAC
2015
ACM
23views Hardware» more  ASPDAC 2015»
10 years 3 months ago
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures
- An approach using a minimum cost maximum flow algorithm is proposed for fault-tolerant topology reconfiguration in a Network-on-Chip system. Topology reconfiguration is converted...
Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shao...
ASPDAC
2015
ACM
26views Hardware» more  ASPDAC 2015»
10 years 3 months ago
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis
Abstract—The emerging nonvolatile memory (NVM) technology can potentially change the landscape of future IC designs with numerous benefits, such as high performance, low leakage...
Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie 0001,...
Hardware
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