ICCD
1995
IEEE
15 years 4 months ago
1995
IEEE
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
80
Voted
ICCD
1995
IEEE
15 years 4 months ago
1995
IEEE
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...
69
Voted
ICCD
1995
IEEE
15 years 4 months ago
1995
IEEE
106
click to vote
ICCD
1995
IEEE
15 years 4 months ago
1995
IEEE
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
104
Voted
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
92
Voted
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
121
click to vote
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
83
Voted
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
113
click to vote
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...