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» Compaction Schemes with Minimum Test Application Time
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ATS
2001
IEEE
137views Hardware» more  ATS 2001»
13 years 8 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
13 years 11 months ago
A diagnosis algorithm for extreme space compaction
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...
Stefan Holst, Hans-Joachim Wunderlich
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
13 years 7 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
13 years 9 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
Irith Pomeranz, Sudhakar M. Reddy
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
13 years 7 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy