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» Oscillation ring based interconnect test scheme for SOC
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ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Oscillation ring based interconnect test scheme for SOC
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
13 years 10 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
13 years 9 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
SLIP
2005
ACM
13 years 10 months ago
Multilevel full-chip routing with testability and yield enhancement
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang...
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...